The present invention relates to a data processing apparatus and, more particularly, to a data processing apparatus controlled by microprograms stored in a control storage.
In order to improve processing performance, a conventional data processing apparatus of this type employs a so-called horizontal type microinstruction system. In this system, a large bit configuration is employed to enhance a function of single step execution of microinstructions constituting a microprogram to realize parallel processing.
Especially for basic instructions which are used frequently, a hardware structure can be optimized to maximize the features of the above horizontal type microinstructions, and hence the number of steps for a microprogram is considerably decreased.
In contrast to this, in other instructions such as many kinds of control instructions, or list processing instructions where data or main storage are repeatedly processed, the operation is sequential. In these instructions even if advanced horizontal type microinstructions are used, the number of microinstructions to be executed in one step is small and there are a large number of unused microinstruction fields, i.e., the parallel processing performance is low. For this reason, such a data processing apparatus employs a hierarchical structure for executing various control instructions by using an instruction program constituted by the above-mentioned basic operation instructions, thereby increasing the utilization efficiency of a control storage for storing a microprogram in the word direction.
A conventional data processing apparatus has an arrangement shown in FIG. 1, i.e., comprises a main storage 1, an instruction fetch circuit 2, an instruction analyzing memory 3 (identifying means), a control storage circuit 4 (executing means), an arithmetic circuit 5, and an exception handler 8.
The main storage 1 comprises a software program section 11 (second storage means) for storing a software program for performing predetermined processing, and an instruction program section 12 (first storage means) for storing a plurality of instruction programs described by first type instructions.
The arithmetic circuit 5 is controlled by the control storage circuit 4 to perform various operations by using a microprogram for realizing a function defined by the first type instructions (to be described later).
The address of software program stored in the software program section 11 of the main storage 1 is generated by an instruction counter 25 and a serial address generating circuit 24 in an instruction fetch circuit 2, and is read out from the main storage 1 by an address held in an instruction address register 21. The readout software program is then stored in an instruction buffer register 22.
Note that instruction fetch is generally performed by a so-called prefetch method wherein when a given instruction is actually executed, the instruction has already reached the instruction buffer register.
First type instructions to be realized by a microprogram in a control storage 41 will be described below. In this case, first type instructions are basic instructions to which the effect of parallel processing of horizontal type microinstructions can be maximized. Generally, the frequency that such instructions are used in a software program is very high. Note that the first type instructions can be used in an instruction program or a software program.
An instruction code portion 221 of the instruction stored in the instruction buffer register 22 is supplied to the instruction analyzing memory 3. Control data 31 to 33 are then read out from the instruction analyzing memory 3 as initial values required to control a microprogram for the instruction. Data other than the instruction code portion 221 in the instruction buffer register 22 is supplied to the branch address generating circuit 23 as an operand.
The control data 32 is data representing whether the corresponding instruction is a first or second type instruction, and is supplied to a microinstruction sequencer 42 of the control storage circuit 4.
If the control data 32 represents that the instruction is a first type instruction, the microinstruction sequencer 42 supplies the control data 31 to the control storage 41 as the start address of a microprogram for executing this instruction, and reads out a microcode from the address of the control storage 41. The readout microcode is temporarily held in the microinstruction register 44 and is supplied therefrom to the arithmetic circuit 5.
Note that this microcode includes a method of determining next microinstruction address, or next microinstruction address itself. When the microinstruction sequencer 42 receives this address from the microinstruction register 44, the next microinstruction is read out. Thereafter, the data processing apparatus sequentially executes a target microprogram in the above-described manner.
Second type instructions to be realized by an instruction program constituted by the first type instructions will be described below. In this case, second type instructions are instructions where a small effect of parallel processing is expected using a microprogram consisting of horizontal type microinstructions, and where microinstructions are rather used like vertical type microinstructions. Note that the second type instructions can only be used in a software program, not in an instruction program.
If the control data 32 from the instruction analyzing memory 3 represents that the instruction is a second type instruction, the microinstruction sequencer 42 stops reading out a microinstruction from the control storage 41 to the microinstruction register 44. A microcode of NOP (no operation) is held in the microinstruction register 44, and the operation of the arithmetic circuit 5 is temporarily interrupted.
At the same time, the control data 32 is supplied to the branch address generating circuit 23. The circuit 23 then outputs the control data 33 as the start address of an instruction program for executing this instruction to the instruction address register 21 through the selector 27 so as to cause the register 21 to hold the start address of the instruction program. By using this address, the data processing apparatus starts reading out the instruction program from the instruction program section 12 of the main storage 1. As a result, the first instruction of the instruction program is stored in the instruction buffer register 22.
In addition, the control data 32 designates an instruction counter saving register 26 (saving means) to store the value (i.e., the address of the second type instruction) of an instruction counter 25 when second type instruction is at first read out from the main storage 1.
When a second type instruction B1 is to be executed by an instruction program described by first type instructions Aa to Ad as shown in FIG. 2, the first instruction Aa is stored in the instruction buffer register 22. Note that a software program in FIG. 2 is constituted by first type instructions A1 to A4 and the second type instruction B1.
Since the instruction Aa is of a first type, it is executed by the microprogram of the control storage 41. Similarly, the instructions Ab and Ac of the instruction program are executed by the microprogram of the control storage 41.
Although the instruction Ad is of a first type, it is the last instruction of the instruction program for executing the second type instruction B1 and serves to return the flow of processing to the instruction A3 next to the instruction B1 in the sequence of the original software program.
That is, the instruction Ad is defined as a relative branch instruction based on an address held in the instruction counter saving register 26. In this case, since the value of the instruction counter 25 when the second type instruction B1 is read out is held in the instruction counter saving register 26, if the instruction word length of the second type instruction B1 is set as a displacement of the relative branch instruction, the instruction address of the instruction A3 next to the second type instruction B1 is generated by the branch address generating circuit 23 in the instruction sequence. Thereafter, this instruction address is held in the instruction address register 21 through the selector 27.
At the same time, by using the address held in the instruction address register 21, the data processing apparatus starts reading out the instruction A3 from the software program section 11 of the main storage 1. The instruction A3 read out from the software program section 11 is stored in the instruction buffer register 22.
Since the instruction A3 is of a first type, it is executed by the microprogram stored in the control storage 41. Subsequently, instructions of the software program are sequentially executed.
The exception handler 8 is normally started when an exception is detected during execution of an instruction read out from the main storage 1 so as to generate an exception message and signal it to the software. In this case, an exception means an abnormal situation occurring during execution of a program, e.g., a software error. This exception message includes the address of an instruction upon occurrence of the exception as well as parameters determined by a type of exception. As the address of the instruction upon occurrence of the exception, the content of the instruction counter 25 at the time when the exception occurs is used. In the exception handler 8, the exception message is prepared by the contents of the instruction counter 25. The preparation of this exception message is generally called exception processing.
In the conventional data processing apparatus, however, if an exception occurs during the execution of the second type instruction B1 to be realized by the instruction program described by the first type instructions Aa to Ad, the addresses of the first type instructions Aa to Ad which are actually executed, i.e., the contents of the instruction counter 25 at the time when the first type instructions Aa to Ad are executed, are used as the address of an instruction upon occurrence of the exception, although the address of the second type instruction B1 should be used as the address of the instruction upon occurrence of the exception.